The present invention relates generally to an apparatus for testing semiconductor devices, and more particularly to an apparatus providing dual temperature zone dynamic wafer-level burn-in of semiconductor devices.
Testing of semiconductor devices during the numerous steps involved in their fabrication occurs at various points along the process to determine proper circuit operability. Two of the more prevalent places to conduct such electrical tests are first at the wafer level, where an integrated circuit (IC) semiconductor device is formed, along with hundreds of others, on a six, eight or twelve inch diameter circular wafer of doped silicon, and second, at the IC level, where individual ICs, known singularly and collectively as xe2x80x9cdiexe2x80x9d and xe2x80x9cdicexe2x80x9d respectively, are cut from the wafer and tested either in a xe2x80x9cbarexe2x80x9d or xe2x80x9cencapsulatedxe2x80x9d state prior to shipping. A critical part of the first type of testing (i.e.: wafer level) involves so-called xe2x80x9cprobexe2x80x9d testing, where connections between each interconnect, or pad, on a device on a wafer and the testing apparatus are temporarily made to provide a communication path through which preprogrammed test signals are passed.
Once the ICs are separated from the wafer, an elevated temperature xe2x80x9cburn-inxe2x80x9d operation is employed to subject the IC to a further battery of tests, thus providing a better indication that the device will function for its intended purpose. Burn-in testing is used to accelerate the identification and isolation of semiconductor devices prone to infant mortality failure mechanisms. During elevated-temperature burn-in testing, stable, precise control of the test chamber is required to ensure, among other things, that adequate impurity migration (which accounts for a significant portion of device infant mortality) is accounted for. However, burn-in testing can be a significant factor in the cost of processing of semiconductor devices. In an era where customer demands to simultaneously increase semiconductor reliability and reduce prices continues apace, manufacturers have been forced to look to increasingly innovative ways to lower the expense of device manufacture while still providing the high-quality products their customers have come to expect.
Traditional burn-in testing has been at the packaged device level, where the use of specialized burn-in boards and sockets is prevalent. Properly engineered boards and sockets, with their complex interconnection schemes and setup, increases testing time and expense. Thus, wafer level burn-in testing can provide a much quicker, less expensive way to determine if a significant number of ICs on a single wafer are worthy of being diced, individually packaged, and then subjected to more detailed operational tests. Dynamic burn-in testing at the wafer level is one of the ways, along with static and full-functional, or xe2x80x9cintelligentxe2x80x9d burn-in, to maximize the likelihood that a batch of semiconductor devices will survive in an end-use product, while keeping the costs to a minimum.
However, the emergence of wafer level testing has not alleviated all of the problems of die level testing. Current wafer burn-in approaches have wafers connected to rack or oven mounted control system tester/drive electronics. If a portion of the test electronics experiences a malfunction, the entire oven must be shut down to remove or repair the defective electronic module. Additional down-time can result from routine thermal circuit connections made each time a cassette holding a wafer under test is inserted into a rack or oven. For example, when a single (i.e.: non-removable) fixture with multiple temperature control feed lines is utilized, such an approach is inconvenient and time-consuming from a test standpoint, as each time a wafer needs to be inserted or removed from the test area, the thermal circuits attached to the wafer cassette must be disconnected, as the integral nature of the wafer cassette and housing necessitate removal of both to access and remove the wafer. The potential for damage to the connectors under such an approach is great, especially after repeated use.
Testing systems are used in many of the stages of the semiconductor fabrication process. In some instances, these stages are carried out over numerous individual machines, while in others, within a single integrated apparatus. Inside wafer level burn-in systems are coming to market. In such systems, wafers are supported in a wafer cassette that secures the wafer under test to maintain precise positional control, thus permitting proper alignment between the individual dies on the wafer and the control electronics. Precise temperature control of wafers under test is required to ensure that actual operating conditions to which an individual die will eventually be exposed in service are accurately replicated. Thermal control systems employing water, air and combinations thereof are both under development and coming to market, in order to keep temperatures in the test area stable for just such purposes. Typically, the test housing in these systems contain the support base, wafer and wafer test fixtures, as well as thermal circuitry. The fluid is routed through thermal circuit penetrations in the support structure walls of the test housing, and is used as a heat transfer mechanism for all of the parts within the housing. It must be pointed out that a thermal circuit responsive to the aggregate needs of the entire cassette may not be suitable to the needs of just the wafer being tested.
In addition, the test electronics are located away from the article being tested, with connection to their remote location effected through coupling cables or the like. This remote positioning of the test electronics inhibits the ability of the burn-in test to adequately support the increasingly faster modem electronic circuits, many of which have a clock time of such short duration that the travel time to and from the remote test electronics is greater than the time between clock cycles. Higher inductance and capacitance occurs when signals must pass through long lines to remotely-spaced electronic devices. This leads to less sharp, well-defined signal transitions, which lead to a compromise in signal integrity. However, merely placing the test electronics adjacent the wafer cassette, without consideration of the wildly varying thermal needs of the test electronics, would only serve to exacerbate an already-perplexing thermal management problem for the wafer under test, as well as potentially jeopardizing sensitive electronic devices.
Accordingly, the need exists in the art for a system which can provide inexpensive, compact and reliable support for wafers during burn-in, especially permitting independent temperature regimes to be tailored to the particular testing needs of the wafer and test electronics, while simultaneously facilitating quick insertion and removal of the wafers under test.
The present invention satisfies the aforementioned need by providing a system which utilizes a separable wafer cassette and base, on-board test electronics, and a plurality of independent temperature control means for the wafer under test and the test electronics. The stackable, modular features of a wafer cassette separable from a stationary base ensure greater system flexibility to meet myriad testing requirements by facilitating wafer interchangeability without having to disconnect and reconnect the thermal circuits each time a wafer is changed. This is made possible in the present invention by including the thermal circuits and their connectors as integral parts of the base, which is in turn fixed to a chassis in the oven or rack. Moreover, the on-board mounting and attendant close proximity of the test electronics to the wafers being tested ensures maximum test performance at rapid test speeds, as well as a compact package, which is critical when such a package is to be enclosed in the tight confines of a burn-in oven.
According to an aspect of the present invention, a wafer burn-in cassette support comprises at least a stationary wafer temperature control base which houses a plurality of substantially adjacent compartments. In the present context, a xe2x80x9ccompartmentxe2x80x9d is any structural member that includes at least partial containment of components disposed therein. This would include, for example, any box- or canister-like structure, either with or without an enclosing lid or top. As used here, and throughout the remainder of this disclosure, the term xe2x80x9csubstantiallyxe2x80x9d to describe a relationship between elements in a device means approximately, but does not have to include an exact, precise or complete relationship. For example, a relatively thin space between the individual compartments could accommodate an insulative medium therebetween, such as air, an inert gas, foam, or other low thermal conductivity material and still be consistent with the instant meaning of substantially adjacent.
This aspect further includes thermal circuits with externally accessible connectors that penetrate the walls of the plurality of compartments of the base, while one of the plurality of compartments includes a vacuum interconnect for securing a wafer to be tested, as well as an electric heater interconnect, both of which include externally accessible connectors. The thermal circuits are designed to operate independently, so that a first thermal circuit could maintain the environment within one of the compartments at one temperature, while a second thermal circuit could maintain a separate, different temperature level in another. Separate, conventional manual or feedback-based thermostatic control means could be employed for each circuit, thus ensuring their autonomy. The xe2x80x9cdual zonexe2x80x9d approach of the present invention therefore allows the wafer under test to be at one temperature, while the nearby test electronics are maintained at another. The use of multiple zones, plus combining the thermal circuit with an electric wafer heater, allows precise control over the temperature in the compartments, with the thermal circuit providing the rough, coarse control, and the electric wafer heater providing the fine-tuning. This approach alleviates the control system cycling (and related hysteresis) problems associated with having various disparate pieces of equipment in a burn-in oven, which are susceptible to different thermal absorption and radiative response times than those of the thin wafers under test. The system of the present invention provides strict, precise control over the test temperature, thus ensuring a more accurate test of the wafer.
According to another aspect of the present invention, a wafer burn-in cassette comprises, in a stacked, aligned, sandwich-like construction, at least a wafer burn-in board assembly, including a platform, on-board wafer test electronics, an electrical test interface connector between the test electronics and external electrical devices, a wafer interconnect assembly with integral wafer test interconnect probes and temperature probes, a wafer test area with an integral aperture through which contact between the aforementioned probes and the surface of the wafer under test is made, and a wafer chuck, which holds the wafer in a spaced, axially aligned relationship between the vacuum source, the heating and cooling source and the aforementioned wafer test area. A platform, as used herein, is a rigid main support member upon which other components may be stacked or mounted. A platform can be configured generally as a tray or plate, with optional gripping, handling or mounting surfaces. This integrated approach of attaching the test electronics and the wafer under test to a common support member allows for a compact mounting and dismounting arrangement. In addition, the close proximity of the test electronics permits a much more rapid transfer of data between it and the individual devices on the wafer, thus ensuring compatibility with sharper signal transitions and rapid test rates.
In still another aspect of the invention, a combination of alignment features are built into the assembly comprising the wafer burn-in cassette and wafer burn-in cassette base to maximize the potential for proper wafer-to-probe alignment. In the cassette section, rough alignment fixtures present on the respective mating surfaces of the aforementioned wafer test area and wafer chuck ensure properly stacked alignment of the individual elements. The use of vacuum mounting further guarantees that once the wafer is mounted, it will not shift during the test. The precise juxtaposition of the wafer under test and the probes to which the individual pads or contacts on the wafer are to be placed in electrical communication is thus ensured by the combination of the alignment fixtures and the provided vacuum. Other embodiments of the cassette may effect alignment via fiducial or visual means. In the base section, the height in the stackwise direction between the substantially adjacent support compartments is different by an amount substantially equal to the thickness of the aforementioned wafer chuck. Thus, the removable wafer cassette with wafer in a wafer chuck is mounted to the base in such a way as to leave no significant vertical gaps that could adversely effect the cassette-to-base connection.
In yet another aspect of the present invention, the wafer interconnect assembly of the wafer cassette further includes a flex film interconnect that avoids electrical connection malfunctions by providing a generally flat, permanently connected direct signal path via parallel, internal wiring channels embedded in a thin sheet of flexible material (such as polyamide plastic) that extends between the aforementioned probes and the wafer test electronics. The chief advantage of the flex film""s thin profile is that it allows these same test electronics to be close to the wafer under test, which permits much more rapid test speeds, and information transfer rates faster than hitherto possible, thereby facilitating data communication from the wafer test interconnect probes located on the wafer interconnect assembly. Thus, a more compact and functional modular burn-in test package is realized.
According to still another aspect of the present invention, the base is designed to be separable from the attached wafer cassette such that upon removal of the cassette, the base, and all of its electrical and thermal connections need not be disconnected, thus minimizing down time and inconvenient delays. As defined herein, the term xe2x80x9cconnectedxe2x80x9d is extended to not just include structures that are bolted, screwed, latched, hinged, fastened, glued, nailed and related approaches, but also to those that through a contiguous relationship are confined in their relative movement to one another though a stacked sandwich-like arrangement. An advantage of the system of the present invention is that its two-part construction, with a removable wafer cassette on top of a stationary base designed to be fixed to the chassis of a semiconductor testing system, is that wafers can be inserted or removed with minimal intrusion to the operation of the thermal control portions of the heating and cooling apparatus. Much of this is due to the thermal circuits being mounted to the stationary base rather than the removable wafer cassette such that they need not be removed each time a wafer is changed. An additional benefit to this configuration is that by minimizing the number of times a user must connect or disconnect thermal circuit fittings, the risk of harm to either the user or adjacent sensitive electronic and plumbing equipment is minimized.
These and other objects and advantages of the invention will be apparent from the following description, the accompanying drawings, and the appended claims.